In communications systems where a transmitter sends information symbols to a receiver over time, there is a fundamental requirement that the receiver and transmitter operate according to a common clock. The receiver generally knows the nominal value of the transmission frequency, but the receiver clock is never truly synchronized with the transmitter clock. Thus, the receiver needs to recover the clock associated with the received signal from the signal itself. This problem of recovering the correct timing information from the received signal is called timing recovery or clock synchronization.
A magnetic recording system may be viewed as a communications system if the write head is viewed as a transmitter and the read head is viewed as the receiver. In magnetic recording, the desire to push recording densities higher has caused today's recording devices to operate at low signal-to-noise ratios (SNR) and with more sophisticated coding algorithms, making timing recovery more challenging. An analog signal produced at the read head is sampled to produce a plurality of samples. Traditional timing recovery architectures include a timing error detector that processes the received samples to produce a quantity that is a measure of the timing phase error. This quantity is further passed through a loop filter to produce a correction signal that is used to control the sampling timing, for example by driving a sampler through a voltage controlled oscillator (VCO). The system is decision directed, i.e., the detected bits are used by the timing recovery algorithm with the assumption that they are error free. A commonly used timing error detector is the Mueller and Müller (MM) detector.
Under ideal operation, the timing phase is updated by the timing recovery algorithm in a way such that the received signal is sampled at the proper locations. However, noise in the system can sometimes cause incorrect timing updates. For example, suppose that errors jn in the timing updates accumulate over several hundreds of bits to produce a net delay of one bit. There will certainly be several detection errors during this interval, but at the end of the interval, the detected bits will become error free but delayed by one bit. The result is that the timing error detector will not detect this one-bit offset in the sampling phase because it is decision directed and operates under the assumption that the decision bits are correct. Thus, any timing recovery that uses a decision directed approach suffers from the above phenomenon called cycle slip.
More generally, the timing phase can jump behind or ahead of the correct sampling phase by an integer number of bits and cause a cycle slip. The MM method performs quite well at high SNRs where the cycle slip rates are generally very low. Then the resulting bit error rates are nearly equal to that of the perfect timing case. However, at lower SNRs, the system is plagued by cycle slips, and the bit error rate rises.
Consequently, there is a need for a timing recovery technique that can be used in magnetic recording devices and other communications devices that operate at low SNRs.